Stacked memory device system interconnect directory-based cache coherence methodology
US11741012B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2020 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Sep 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a plurality of host processors and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.