Quadrature error correction circuit and semiconductor memory device including the same
US11742016B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Feb 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.