Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory
US11742045B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2021 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Feb 24, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.