Method of reducing voids and seams in trench structures by forming semi-amorphous polysilicon
US11742208B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2020 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Jun 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.