Diffusion barrier layer for conductive via to decrease contact resistance
US11742291B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2022 |
| Grant date | Aug 29, 2023 |
| Priority date | — |
| Expiry date | Jun 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments relate to a semiconductor structure including a method for forming a semiconductor structure. The method includes forming a lower conductive structure within a first dielectric layer over a substrate. An upper dielectric structure is formed over the lower conductive structure. The upper dielectric structure comprises sidewalls defining an opening over the lower conductive structure. A first liner layer is selectively deposited along the sidewalls of the upper dielectric structure. A conductive body is formed within the opening and over the lower conductive structure. The conductive body has a bottom surface directly overlying a middle region of the lower conductive structure. The first layer is laterally offset from the middle region of the lower conductive structure by a non-zero distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.