Multilayer high-k gate dielectric for a high performance logic transistor

US11742407B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Seung Hoon Sung · Beaverton, US
• Ashish Verma Penumatcha · Hillsboro, US
• Sou-Chi Chang · Portland, US
• Devin Merrill · McMinnville, US
• I-Cheng Tung · Hillsboro, US
• Nazila Haratipour · Hillsboro, US
• Jack T. Kavalieros · Portland, US
• Ian A. Young · Portland, US
• Matthew V. Metz · Portland, US
• Uygar E. Avci · Portland, US
• Chia-Ching Lin · Daxi District, TW
• Owen Loh · Portland, US
• Shriram Shivaraman · Hillsboro, US
• Eric Mattson · Portland, US

Key dates

• Filing date: Dec 2, 2019
• Grant date: Aug 29, 2023
• Expiry date: Dec 12, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/689

Abstract

A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.