Memory system, integrated circuit system, and operation method of memory system
US11747985B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2021 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | Mar 5, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes: a memory core; an error correction circuit suitable for correcting, when a number of one or more errors detected in data read from the memory core is equal to or greater than a threshold value, the detected errors based on an error correction code read from the memory core to produce an error-corrected data; and a data transferring circuit suitable for: outputting, when the detected errors are corrected, the error-corrected data according to a long read latency, and outputting, when the number of the detected errors is less than the threshold value or no error is detected in the read data, the read data according to a short read latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.