Memory, memory system, and operation method of memory system
US11748007B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2021 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | Nov 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes: a non-volatile memory suitable for storing a defect address; a register suitable for receiving and storing the defect address from the non-volatile memory during a boot-up operation, and receiving and storing an address that is input from an exterior during a register access operation; a comparison circuit suitable for comparing the address stored in the register with an address that is input from the exterior to produce a comparison result; redundant memory cells that are accessed according to the comparison result of the comparison circuit and a redundancy activation bit; and normal memory cells that are accessed according to the comparison result of the comparison circuit and the redundancy activation bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.