Systems and methods for performing matrix compress and decompress instructions
US11748103B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2022 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | Feb 20, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.