Patent · US Active

Memory management device, system and method

US11749343B2 · kind B2 · utility

0Cited by

8References

27Claims

0Family size

Assignee

STMicroelectronics International N.V. · NL

Inventors

Nitin Chawla · Noida, IN
Tanmoy Roy · Mountain View, US
Anuj Grover · New Delhi, IN

Key dates

Filing date	Jan 18, 2022
Grant date	Sep 5, 2023
Priority date	—
Expiry date	Jan 18, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG11C2211/561
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.