Three-dimensional memory devices and fabricating methods thereof
US11751385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2020 |
| Grant date | Sep 5, 2023 |
| Priority date | — |
| Expiry date | Feb 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
A method for forming a 3D memory device is provided. The method comprises forming a sacrificial layer on a substrate, forming an alternating dielectric stack on the sacrificial layer, forming a plurality of channel holes vertically penetrating the alternating dielectric stack and the sacrificial layer, and forming a first channel layer in each channel hole. The method further comprises forming a second channel layer on the first channel layer in each channel hole, such that a merging point of the second channel layer is higher than a bottom surface of the alternating dielectric stack. The method further comprises removing the sacrificial layer to form a horizontal trench, and forming a selective epitaxial growth layer in the horizontal trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.