System and method for identifying latent reliability defects in semiconductor devices
US11754625B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2021 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | May 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2894
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for identifying latent reliability defects (LRD) in semiconductor devices are configured to perform one or more stress tests with one or more stress test tools on at least some of a plurality of wafers received from one or more in-line sample analysis tools to determine a passing set of the plurality of wafers and a failing set of the plurality of wafers, perform a reliability hit-back analysis on at least some of the failing set of the plurality of wafers, analyze the reliability hit-back analysis to determine one or more geographic locations of one or more die fail chains caused by one or more latent reliability defects (LRD), and perform a geographic hit-back analysis on the one or more geographic locations of the one or more die fail chains caused by the LRD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.