Chip integration into cavities of a host wafer using lateral dielectric material bonding
US11756848B1 · kind B1 · utility
1Cited by
10References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 17, 2023 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Jan 17, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/96
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.