Chip-stacked semiconductor package with increased package reliability
US11756935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2021 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Oct 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip-stacked semiconductor package includes: a base chip having a base through via; a first chip stacked on the base chip in an offset form, wherein the first chip has a first exposed surface and a first through via electrically connected to the base through via; a first molding layer positioned on the base chip and covering a first non-exposed surface, facing the first exposed surface, of the first chip; a second chip stacked on the first chip in an offset form, wherein the second chip has a second exposed surface and a second through via electrically connected to the first through via; and a second molding layer formed on the first chip and covering a second non-exposed surface, facing the second exposed surface, of the second chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.