Semiconductor device with increased isolation breakdown voltage
US11756992B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 2022 |
| Grant date | Sep 12, 2023 |
| Priority date | — |
| Expiry date | Aug 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor substrate comprising a P-type lightly doped semiconductor layer; an undoped silicon layer formed on the P-type lightly doped semiconductor layer; a first deep trench isolation and a second deep trench isolation formed from an upper surface of the semiconductor substrate to the undoped silicon layer and filled with insulating films; and a first N-type highly doped buried layer formed on the undoped silicon layer, and disposed between the first deep trench isolation and the second deep trench isolation, wherein the undoped silicon layer surrounds bottoms of the first and second deep trench isolations, and has a thickness greater than a thickness of the first N-type highly doped buried layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.