Thin-film transistor embedded dynamic random-access memory with shallow bitline

US11758711B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Yih Wang · Portland, US
• Abhishek A. Sharma · Hillsboro, US
• Tahir Ghani · Portland, US
• Allen B. Gardiner · Portland, US
• Travis W. Lajoie · Forest Grove, US
• Pei-Hua Wang · Beaverton, US
• Chieh-Jen Ku · Hillsboro, US
• Bernhard Sell · Dresden, DE
• Juan G. Alzate-Vinasco · Tigard, US
• Blake C. Lin · Portland, US

Key dates

• Filing date: Mar 17, 2022
• Grant date: Sep 12, 2023
• Expiry date: Mar 17, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/80
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.