Chip packaging structure and manufacturing method thereof
US11764120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2021 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Sep 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/13
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip packaging structure includes a chip, a redistribution layer, a solder ball, an encapsulant, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connected to the active surface and the back surface. The redistribution layer is disposed on the active surface of the chip. The solder ball is disposed on the redistribution layer, and the chip is electrically connected to the solder ball through the redistribution layer. The encapsulant encapsulates the active surface and the back surface of the chip, the redistribution layer, and part of the solder ball. The stress buffer layer at least covers the peripheral surface of the chip. An outer surface of the stress buffer layer is aligned with a side surface of the encapsulant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.