Integrated circuit structure and method
US11764171B2 · kind B2 · utility
1Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2021 |
| Grant date | Sep 19, 2023 |
| Priority date | — |
| Expiry date | Jun 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.