Delay fault testing of pseudo static controls
US11768726B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2021 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Dec 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.