Training and operations with a double buffered memory topology
US11768780B2 · kind B2 · utility
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6References
20Claims
0Family size
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Key dates
| Filing date | Mar 31, 2022 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Mar 31, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1778
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.