Interconnect flow graph for integrated circuit design
US11768990B1 · kind B1 · utility
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18Claims
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Key dates
| Filing date | Jun 29, 2021 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Nov 20, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit design technique utilizes a data structure describing the connections, interconnect routing information of the connections, and bandwidth requirements of the connections in an integrated circuit device to generate an interconnect flow graph having nodes, and edges connecting the nodes. The edges connecting the nodes can reflect the bandwidth requirements of the connections. The interconnect flow graph can be used to optimize and verify the integrated circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.