Power device structures and methods of making
US11769665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2022 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Mar 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67754
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.