Apparatuses exhibiting enhanced stress resistance and planarity, and related microelectronic devices and memory devices
US11769738B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2021 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Sep 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06593
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.