High capacitance MIM device with self aligned spacer
US11769791B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2021 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | May 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.