Enabling stripe-based operations for error recovery at a memory sub-system
US11775179B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2021 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Sep 5, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1435
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A request to program a set of host data items to management units (MUs) of a fault tolerant stripe associated with a memory sub-system is received. A set of memory access operations to be executed at the MUs of the fault tolerant stripe in accordance with the received request is determined. The set of memory access operations include one or more read operations to read data from the MUs of the fault tolerant stripe. The set of memory access operations also include one or more write operations to write the set of host data items and redundancy metadata associated with the set of host data items to MUs of the fault tolerant stripe. A first series of commands corresponding to the one or more read operations of the set of memory access operations is executed. The redundancy metadata associated with the set of host data items is generated based on the data read from the MUs of the fault tolerant stripe during execution of the first series of commands and the set of host data items. A second series of commands corresponding to the one or more write operations of the set of memory access operations is executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.