Juane Li
30Patents
3h-index
19Co-inventors
56Inventor score
Filing activity: Jul 28, 2010 → Dec 6, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8174934B2 | Sound direction detection | Physics | 17 | Active |
| US10404280B2 | Error correction using cyclic code-based LDPC codes | Electricity | 6 | Active |
| US11775179B2 | Enabling stripe-based operations for error recovery at a memory sub-system | Physics | 3 | Active |
| US11038530B2 | Error correction using cyclic code-based LDPC codes | Electricity | 1 | Active |
| US11068336B2 | Generating error checking data for error detection during modification of data in a memory sub-system | Physics | 1 | Active |
| US11847349B2 | Dynamic partition command queues for a memory device | Physics | 0 | Active |
| US12346574B2 | Enabling stripe-based operations for error recovery at a memory sub-system | Physics | 0 | Active |
| US12093564B2 | Partition command queues for a memory device | Physics | 0 | Active |
| US12314608B2 | Dynamic partition command queues for a memory device | Physics | 0 | Active |
| US11080132B2 | Generating error checking data for error detection during modification of data in a memory sub-system | Physics | 0 | Active |
| US11709729B2 | Performing error checking operations on encrypted write data in a memory sub-system | Physics | 0 | Active |
| US11775216B2 | Media access operation command management using media buffers | Physics | 0 | Active |
| US12333154B2 | Reducing bit error rate in memory devices | Physics | 0 | Active |
| US11615214B2 | Cryptographic key management | Physics | 0 | Active |
| US11899972B2 | Reduce read command latency in partition command scheduling at a memory device | Physics | 0 | Active |
| US11934657B2 | Open block management in memory devices | Physics | 0 | Active |
| US11709631B2 | Read-modify-write data consistency management | Physics | 0 | Active |
| US11860732B2 | Redundancy metadata media management at a memory sub-system | Physics | 0 | Active |
| US12164811B2 | Concurrent command limiter for a memory system | Physics | 0 | Active |
| US11929763B2 | Storage error correction using cyclic-code based LDPC codes | Electricity | 0 | Active |
| US12298847B2 | Tracking host-provided metadata in a memory sub-system | Physics | 0 | Active |
| US12254926B2 | Memory device with fast write mode to mitigate power loss | Physics | 0 | Active |
| US11693597B2 | Managing package switching based on switching parameters | Physics | 0 | Active |
| US11698867B2 | Using P2L mapping table to manage move operation | Physics | 0 | Active |
| US11636008B2 | Tracking host-provided metadata in a memory sub-system | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.