Encoded enable clock gaters
US11776599B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 2021 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Sep 24, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device is provided which includes a processor and a data storage structure. The data storage structure comprises a data storage array comprising a plurality of lines. Each line comprises at least one A latch configured to store a data bit and a clock gater. The data storage structure also comprises a write data B latch configured to store, over different clock cycles, a different data bit, each to be written to the at least one A latch of one of the plurality of lines. The data storage structure also comprises a plurality of write index B latches shared by the clock gaters of the lines. The write index B latches are configured to store, over the different clock cycles, combinations of index bits having values which index one of the lines to which a corresponding data bit is to be stored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.