Through silicon via fabrication
US11776849B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2022 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Aug 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One or more embodiments are directed to establishing electrical connections through silicon wafers with low resistance and high density, while at the same time maintaining processability for further fabrication. Such connections through silicon wafers enable low resistance connections from the top side of a silicon wafer to the bottom side of the silicon wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.