Vertical transistors for ultra-dense logic and memory applications

US11777029B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Nazila Haratipour · Hillsboro, US
• I-Cheng Tung · Hillsboro, US
• Abhishek A. Sharma · Hillsboro, US
• Arnab Sen Gupta · Beaverton, US
• Van H. Le · Portland, US
• Matthew V. Metz · Portland, US
• Jack T. Kavalieros · Portland, US
• Tahir Ghani · Portland, US

Key dates

• Filing date: Jun 27, 2019
• Grant date: Oct 3, 2023
• Expiry date: Nov 12, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D99/00

Abstract

A vertical transistor structure includes a material stack having a source material, a drain material, and a channel material therebetween. The vertical transistor structure further includes a gate electrode adjacent to a sidewall of the stack, where the sidewall includes the channel material, and at least a partial thickness of both the source material and the drain material. A gate dielectric is present between the sidewall of the stack and the gate electrode. The vertical transistor structure further includes a first metallization over a first area of the stack above the gate dielectric layer, and in contact with the gate electrode on sidewall of the stack. A second metallization is adjacent to the first metallization, where the second metallization is over a second area of the stack, and in contact with the source material or the drain material.