Anti-fuse memory device, memory array, and programming method of an anti-fuse memory device for preventing leakage current and program disturbance
US11783905B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Sep 8, 2021 |
| Grant date | Oct 10, 2023 |
| Priority date | — |
| Expiry date | Sep 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a driving circuit of an anti-fuse memory device programs a selected anti-fuse memory cell, voltage differences between unselected bit lines and unselected anti-fuse control lines would be eliminated or decreased to an acceptable value by floating unselected anti-fuse control lines or by applying a second control line voltage to the unselected anti-fuse control lines. Leakage currents flowing from unselected bit lines through ruptured anti-fuse transistors of the anti-fuse memory device to the unselected anti-fuse control lines would be decreased or eliminated, and program disturbance would be avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.