Methods and structures for improved electrical contact between bonded integrated circuit interfaces

US11784123B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Richard Vreeland · Beaverton, US
• Colin T. Carver · Hillsboro, US
• William Brezinski · Beaverton, US
• Michael Christenson · Beaverton, US
• Nafees Kabir · Portland, US

Key dates

• Filing date: Feb 22, 2022
• Grant date: Oct 10, 2023
• Expiry date: Feb 22, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2225/06541
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.