Three dimensional circuit systems and methods having memory hierarchies

US11789641B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Scott J. Weber · Piedmont, US
• Jawad B. Khan · Cornelius, US
• Ilya K. Ganusov · San Jose, US
• Martin Langhammer · Calne, GB
• Matthew J. Adiletta · Bolton, US
• Terence J. Magee · San Francisco, US
• Albert Fazio · Los Gatos, US
• Richard Coulson · Portland, US
• Ravi Prakash Gutala · San Jose, US
• Aravind Raghavendra Dasu · Milpitas, US
• Mahesh A. Iyer · Fremont, US

Key dates

• Filing date: Jun 16, 2021
• Grant date: Oct 17, 2023
• Expiry date: Jun 16, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C5/063
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.