Error correction for internal read operations
US11789817B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 2021 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Dec 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for error correction for internal read operations are described. In some memory systems, a memory device may perform an internal read operation, in which the memory device reads data internal to the memory device (e.g., without sending the data to a memory system controller). To detect and correct errors during an internal read operation, the memory device may use an error control circuit on a memory die. The error control circuit on the memory die may operate on the same codeword, including the same data and same parity bits, as an error control circuit at the memory system controller, effectively reusing the stored parity bits for host read operations and internal read operations. To reduce the decoding overhead at the memory device, the error control circuit on the memory die may support detecting fewer errors than the error control circuit at the memory system controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.