Coordinated error correction
US11789818B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Mar 9, 2022 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Mar 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for coordinated error correction are described. A memory device indicates, to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. Based on a result of the comparison, an indication of whether the compared error correction codes match is provided to the external device. The external device uses the indication to detect errors in the received version of the data, to manage data storage in the memory device, or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.