Scott E. Schaefer
148Patents
19h-index
21Co-inventors
86Inventor score
Filing activity: Oct 31, 1990 → Jun 27, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5636173A | Auto-precharge during bank selection | Physics | 179 | Expired |
| US5600605A | Auto-activate on synchronous dynamic random access memory | Physics | 162 | Expired |
| US5666321A | Synchronous DRAM memory with asynchronous column decode | Physics | 136 | Expired |
| US5544124A | Optimization circuitry and control for a synchronous memory device with programmable latency period | Physics | 124 | Expired |
| US5257233A | Low power memory module using restricted RAM activation | Physics | 91 | Expired |
| US5457659A | Programmable dynamic random access memory (DRAM) | Physics | 79 | Expired |
| US5887162A | Memory device having circuitry for initializing and reprogramming a control operation feature | Physics | 73 | Expired |
| US7277333B2 | Power savings in active standby mode | Physics | 69 | Expired |
| US6862202B2 | Low power memory module using restricted device activation | Physics | 64 | Expired |
| US5335201A | Method for providing synchronous refresh cycles in self-refreshing interruptable DRAMs | Physics | 56 | Expired |
| US6438060B1 | Method of reducing standby current during power down mode | Physics | 46 | Expired |
| US5751656A | Synchronous DRAM memory with asynchronous column decode | Physics | 36 | Expired |
| US5229970A | Circuit for synchronizing refresh cycles in self-refreshing drams having timing circuit shutdown | Physics | 30 | Expired |
| US6819599B2 | Programmable DQS preamble | Physics | 29 | Expired |
| US5208779A | Circuit for providing synchronous refresh cycles in self-refreshing interruptable DRAMs | Physics | 28 | Expired |
| US7480792B2 | Memory modules having accurate operating parameters stored thereon and methods for fabricating and implementing such devices | Physics | 25 | Active |
| US5982697A | Method for initializing and reprogramming a control operation feature of a memory device | Physics | 22 | Expired |
| US6836437B2 | Method of reducing standby current during power down mode | Physics | 22 | Expired |
| US7035159B2 | Techniques for storing accurate operating current values | Physics | 20 | Expired |
| US6930949B2 | Power savings in active standby mode | Physics | 18 | Expired |
| US5717639A | Memory device having circuitry for initializing and reprogramming a control operation feature | Physics | 17 | Expired |
| US6111814A | Synchronous DRAM memory with asynchronous column decode | Physics | 17 | Expired |
| US5229969A | Method for synchronizing refresh cycles in self-refreshing DRAMs having timing circuit shutdown | Physics | 17 | Expired |
| US7349269B2 | Programmable DQS preamble | Physics | 16 | Expired |
| US6751159B2 | Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode | Physics | 14 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.