Packaging structure and packaging method of digital circuit
US11791232B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2021 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Jun 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging structure includes: a substrate provided with a through-cavity penetrating up and down, and a metal heat sink on a front surface of the substrate; a bonding chip mounting area and a first passive element mounting area on the front surface, and a flip chip mounting area, a second passive element mounting area and a pin lead mounting area are provided on a back surface of the substrate; a first sealing ring located at the periphery of the bonding chip mounting area and the first passive element mounting area; a first cover plate packaged on the first sealing ring; a second sealing ring located at the periphery of the flip chip mounting area and the second passive element mounting area with the pin lead mounting area being located at the periphery of the second sealing ring; and a second cover plate packaged on the second sealing ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.