Semiconductor package including part of underfill on portion of a molding material surrounding sides of logic chip and memory stack on interposer and method for manufacturing the same
US11791282B2 · kind B2 · utility
0Cited by
10References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 29, 2020 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Jan 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package comprises a substrate; an interposer on the substrate; a first underfill between the substrate and the interposer; at least one logic chip and at least one memory stack on the interposer; and a molding material on the interposer while surrounding a side surface of the at least one logic chip and a side surface of the at least one memory stack. The molding material includes areas having different heights. The first underfill covers a portion of the molding material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.