Power device integration on a common substrate
US11791377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2022 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Apr 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/158
Abstract
A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.