Systems and methods for semiconductor adaptive testing using inline defect part average testing

US11798827B2 · kind B2 · utility

Assignee

• KLA Corporation · US

Inventors

• Robert J. Rathert · Mechanicsville, US
• David W. Price · Austin, US
• Chet V. Lenox · Venus, US
• Oreste Donzella · San Ramon, US
• Kara L. Sherman · Santa Clara, US
• John Robinson · Austin, US

Key dates

• Filing date: May 28, 2021
• Grant date: Oct 24, 2023
• Expiry date: Aug 27, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G05B2219/45031
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Systems and methods for semiconductor adaptive testing using inline defect part average testing are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an I-PAT system, where the plurality of I-PAT scores is generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a weighted defectivity determined by the I-PAT system based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.