Self-aligned trench MOSFET
US11798982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2021 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Dec 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/2527
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.