Multi-level cache coherency protocol for cache line evictions
US11803470B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 22, 2020 |
| Grant date | Oct 31, 2023 |
| Priority date | — |
| Expiry date | Dec 22, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are examples of a system and method to communicate cache line eviction data from a CPU subsystem to a home node over a prioritized channel and to release the cache subsystem early to process other transactions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.