Bipolar transistor structure with emitter/collector contact to doped semiconductor well and related methods
US11804541B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2022 |
| Grant date | Oct 31, 2023 |
| Priority date | — |
| Expiry date | Mar 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/27
Abstract
Embodiments of the disclosure provide a lateral bipolar transistor structure with an emitter/collector (E/C) contact to a doped semiconductor well and related methods. A bipolar transistor structure according to the disclosure may include a doped semiconductor well over a semiconductor substrate. An insulative region is on the doped semiconductor well. A base layer is on the insulative region, and an emitter/collector (E/C) layer on the insulative region and adjacent a first sidewall of the base layer. An E/C contact to the doped semiconductor well includes a lower portion adjacent the insulative region and an upper portion adjacent and electrically coupled to the E/C layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.