Metal interconnect structure and method for fabricating the same
US11810818B2 · kind B2 · utility
0Cited by
3References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 9, 2021 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Sep 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53266
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.