Via for semiconductor device and method
US11810857B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2020 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Aug 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.