Substrate component layout and bonding method for increased package capacity
US11810896B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2021 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Jun 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for substrate component layout and bonding for increased package capacity. According to certain embodiments, a wire-bonding finger strip is disposed between a flip-chip die and a NAND die stack to reduce a keep out zone (KOZ) required for an underfill material dispensed beneath the flip-chip die. To further inhibit the flow of the underfill material and further reduce the KOZ, a solder mask may be placed adjacent to the flip-chip. According to certain embodiments, there may be at least three sides of the flip-chip that may have such an adjacent solder mask placement. The three sides of the flip-chip according to such embodiments may be those non-adjacent to the wire-bonding finger strip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.