Semiconductor-on-insulator field effect transistor with performance-enhancing source/drain shapes and/or materials
US11810951B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2021 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Feb 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
Disclosed are a semiconductor structure and method of forming the structure. The structure includes a field effect transistor (FET) with a channel region between source/drain regions that extend through a semiconductor layer and into an insulator layer, that include a first portion in the insulator layer, and a second portion on the first portion in the semiconductor layer and, optionally, extending above the semiconductor layer. The first portion is relatively wide, includes a shallow section below the second portion, and a deep section adjacent to the channel region and overlayed by the semiconductor layer. The uniquely shaped first portion boosts saturation current to be boosted to allow the height of the second portion to be reduced to minimize overlap capacitance. Optionally, each source/drain region includes multiple semiconductor materials including a stress-inducing semiconductor material grown laterally from the semiconductor layer to improve charge carrier mobility in the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.