Patent · US Active

Channel formation for three dimensional transistors

US11810980B2 · kind B2 · utility

0Cited by

4References

21Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Chieh-Jen Ku · Hillsboro, US
Pei-Hua Wang · Beaverton, US
Bernhard Sell · Dresden, DE
Martin M. Mitan · Beaverton, US
Leonard C. Pipes · Beaverton, US

Key dates

Filing date	Jun 28, 2019
Grant date	Nov 7, 2023
Priority date	—
Expiry date	Mar 6, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/6755
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Embodiments herein describe techniques for a transistor above a substrate. The transistor includes a channel layer above the substrate. The channel layer includes a first channel material of a first conductivity. In addition, the channel layer further includes elements of one or more additional materials distributed within the channel layer. The channel layer including the elements of the one or more additional materials has a second conductivity different from the first conductivity. Other embodiments may be described and/or claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.