Systems and methods for detecting erratic programming in a memory system
US11817157B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2021 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | Jan 14, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The storage device that includes a non-volatile memory with a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops. The programming loops include applying a programming pulse to a selected word line of the plurality of word lines. The programming loops also include applying a verify pulse VN to the selected word line to simultaneously verify a lower tail of the memory cells being programmed to a data state N and an upper tail of the memory cells that have been programmed to a data state N−1. The data state N−1 has a lower voltage threshold than the data state N.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.