Molded semiconductor package with high voltage isolation
US11817407B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2022 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | May 17, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/301
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A molded semiconductor package includes: a semiconductor die attached to a substrate, the semiconductor die having a bond pad at a first side of the semiconductor die which faces away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a part of the bond pad exposed by an opening in the insulating layer; a mold compound encasing the semiconductor die; and an electrically insulative material filling the opening in the insulating layer and sealing the part of the bond pad exposed by the opening in the insulating layer. The electrically insulative material separates the mold compound from the part of the bond pad exposed by the opening in the insulating layer. A corresponding method of producing the molded semiconductor package also is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.