Erasable programmable single-poly non-volatile memory cell and associated array structure
US11818887B2 · kind B2 · utility
1Cited by
4References
13Claims
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Key dates
| Filing date | Mar 4, 2022 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | Jul 9, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.